Self-aligned double patterning (SADP) techniques, are currently used in ultra-high density integrated circuits to provide an electrical interconnection system which includes multiple arrays of parallel metal lines disposed in several levels of dielectric layers. The dielectric layers are typically interconnected through a system of metalized vias. Conventionally, within an array of metal lines, the direction longitudinal to the metal lines is designated the “Y” direction and the direction perpendicular, or lateral, to the metal lines is designated the “X” direction.
Such SADP techniques typically involve the use of a lithographic mask (designated herein as a “mandrel mask”) to pattern and print an array of longitudinally extending parallel mandrels onto a top surface of a hardmask layer. The longitudinal direction of the mandrels defines the Y direction of the array. Spacers are then formed on both sidewalls of each mandrel. The spacers are considered to be self-aligned in the X direction (perpendicular to the Y direction) because the spacing between the spacers in the X direction was defined by the sidewalls of the existing mandrels.
Each combination of mandrel and associated spacer pair is separated by exposed parallel portions of the hardmask layer, which are absent any overlaying mandrels or spacers. The mandrels are patterned down into a dielectric layer of the integrated circuit to form mandrel metal lines. The exposed portions of the hardmask layer are also patterned down into the dielectric layer to form non-mandrel metal lines. Therefore, each array of parallel metal lines in an interconnection system formed using an SADP process will include alternating mandrel and non-mandrel metal lines, which are separated by a distance equal to the width of the self-aligned spacers.
In order to provide functionality between devices, such as transistors, capacitors and the like, in the integrated circuit, a plurality of cuts must be lithographically patterned into the mandrel and non-mandrel metal lines of an array at specific locations to direct current flow between the dielectric layers and the devices. Generally, another lithographic mask (designated herein as a “mandrel line cut mask”) is used to pattern such mandrel cuts into the mandrel metal lines. Also generally yet another lithographic masks (designated herein as a “non-mandrel line cut mask”) is used to pattern such non-mandrel cuts into the non-mandrel metal lines.
Accordingly, a typical SADP process for patterning arrays of metal lines in a complex interconnection system for an integrated circuit requires at least three masks: a mandrel mask, a mandrel line cut mask, and a non-mandrel line cut mask. Development and use of such masks requires complex, state of the art technology, especially when lithographically printing aggressively small features in such technology class sizes as the 14 nanometer (nm) class and beyond. Therefore it is desirable to keep the number of masks to a minimum due to the large costs associated with the development and use of such masks.
However, there is often a requirement for multiple cuts located closely together along the Y direction (the longitudinal direction) of a single mandrel or non-mandrel line within an array. Problematically the prior art optical limit for lithographically patterning two cuts next to one another with the same cut mask is about 100 nanometers from center to center of the cuts. Therefore, if such cuts are located less than 100 nm apart in the Y direction on the same line, each cut will require a separate cut mask using prior art lithographic techniques. Moreover, costs and logistic complexities increase rapidly as the number of closely located cuts increase beyond two per line and, therefore, the number of cut masks also increase. Additionally, the cuts in a single line are not self-aligned in the Y direction, which exacerbate lithographic tolerance issues.
In many devices, such as static random access memory (SRAM) cells and other similar logic devices, closely located multiple cuts per single line are required in both the mandrel lines and non-mandrel lines of an array.
Accordingly, there is a need to be able to provide multiple cuts in a single metal line of an array of metal lines for an integrated circuit that are located closer than 100 nm apart in the Y direction through the use of a single cut mask. Additionally, there is a need to provide self-aligned cuts located closer than 100 nm in the Y direction. More specifically, there is a need to be able to provide multiple cuts in both the mandrel and non-mandrel lines of an array of metal lines for an integrated circuit that are located less than 100 nm apart and self-aligned in the Y direction through the use of a single mandrel line cut mask and/or a single non-mandrel line cut mask.